HAKKEE JUNG. Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric. International Journal of Engineering and Technology Innovation, [S. l.], v. 14, n. 2, p. 189–200, 2024. DOI: 10.46604/ijeti.2023.12887. Disponível em: https://ojs.imeti.org/index.php/IJETI/article/view/12887. Acesso em: 26 may. 2024.