Performance Evaluation for Stacked-Layer Data Bus Based on Isolated Unit-Size Repeater Insertion


  • Chia-Chun Tsai Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan


stacked-layer chip, 3D data bus, unit-size repeater, average access time


The data bus of a stacked-layer chip always supports that data of a program are frequently running on the bus at different timing periods. The average data access time of a data bus to the timing periods dominates the program performance. In this paper, we proposed an evaluated approach to reconstruct a 3D data bus with inserted unit-size repeaters to motivate that the average data access time of the bus on a complete timing period can speed up at least 10%. The approach is trying to insert a number of unit-size repeaters into bus wires along the path of a source-sink pair for isolating extra capacitive loadings at each timing period to reduce their access time. The above process is repeated until no any improvement for each access time. Each inserted repeater with just one unit size due to the limited space of a chip area and the minor reconstruction of a data bus in practical. The approach has the advantages of uniform repeater insertion, less extra area occupation, and simplified time-to-space tradeoff. Experimental results show that our approach has the rapid capable evaluation for a stacked-layer data bus within one millisecond and the saving in average access time is up to 50.81% with the inserted repeater sizes of 70 on average.


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How to Cite

C.-C. Tsai, “Performance Evaluation for Stacked-Layer Data Bus Based on Isolated Unit-Size Repeater Insertion”, Adv. technol. innov., vol. 4, no. 3, pp. 197–209, Jun. 2019.