Golden-Finger and Back-Door: Two HW/SW Mechanisms for Accelerating Multicore Computer Systems
Continuously requirements of high-performance computing make the computer system adopt more processors
within a system to improve the parallelism and throughput. Although multiple processing cores are implemented in
a computer system, the complicated hardware communication mechanism between processors will decrease the
performance of overall system. Besides, the unsuitable process scheduling mechanism of conventional operating
system can not fully utilize the computation power of additional processors. Accordingly, this paper provides two
mechanisms to overcome the above challenges by using hardware and software mechanisms, respectively. In
software aspect, we propose a tool, called Golden-Finger, to dynamically adjust the scheduling policy of the process
scheduler in Linux. This software mechanism can improve the performance of the specified process by occupying a
processor solely. In hardware aspect, we design an effective hardware mechanism, called Back-Door, to
communicate two independent processors which can not be operated together, such as the dual PowerPC 405 cores
in the Xilinx ML310 system. The experimental results reveal that the two mechanisms can obtain significant
J. Aas, Understanding the Linux 184.108.40.206 CPU Scheduler, Silicon Graphics, Inc., 2005.
R. Love, Linux Kernel Development, SAMS, Developer Library Series, 2003.
E. Piel, P. Marquet, J. Soula, and J.L. Dekeyser, “Asymmetric Real-Time Scheduler on Multi-Processor Architecture”,
th International Parallel and Distributed Processing Symposium, Apr. 2006, pp. 25-29.
G. E. Allen and B. L. Evans. “Real-time sonar beamforming on workstations using process networks and POSIX threads”,
IEEE Transactions on Signal Processing, pp. 921-926, Mar. 2000.
K. Morgan, “Preemptible Linux: A reality check”, Cuba: MontaVista Software, Inc., 2001.
J. D. Valois. “Implementing lock-free queues”. In Proceedings of the Seventh International Conference on Parallel and
Distributed Computing Systems, Oct. 1994.
I-Tao Liao, Koan-Sin Tan, Shau-Yin Tseng, and Wen-Feng Chen, “Interprocessor Communication for PAC”, ITRI SoC
Technical Journal, No.002.
Intel Corp. Intel® Core™ Microarchitecture. http://www.intel.com/technology/architecture/coremicro/index.htm
IBM Corp. The Cell Architecture. http://www.research.ibm.com/cell
N. Njoroge, S. Wee, J. Casper, J. Burdick, Y. Teslyar, C. Kozyrakis, and K. Olukotun, “Building and Using the ATLAS
Transactional Memory System”, 12th International Symposium on High-Performance Computer Architecture (HPCA),
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